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Setup Time And Hold time|STA|Delays in Digital Circuit
Dear readers Attention please, read the article carefully first.
I have recorded a video that will be helpful for you to understand the concept of Setup and Hold time concept, but before watching the video it is recommended you that please read the article to take an overview of all delays. The video link is given at the bottom of the article. Happy learning.....
TYPES OF DELAY
Propagation delay
Contamination Delay
Setup Time
Hold time
(1) Propagation delay (Worst case delay): The propagation delay of a logic gate is defined as the time it takes for the effect of change in input to be visible at the output. In other words, propagation delay is the time required for the input to be propagated to the output. Normally, it is defined as the difference between the times when the transitioning input reaches 50% of its final value to the time when the output reaches 50% of the final value showing the effect of input change. Here, 50% is defined as the logic threshold where output is assumed to switch its states.
Propagation delay example: Let us consider a 2-input AND gate as shown in Figure 1, with input ‘I2’ making the transition from logic ‘0’ to logic ‘1’ and 'I1' being stable at logic value '1'. In effect, it will cause the output ‘O’ also to make a transition. The output will not show the effect immediately but after a certain time interval. The timing diagram for the transitions is also shown. The propagation delay, in this case, will be the time interval between I2 reaching 50% and rising to 'O' reaching 50% mark while rising as a result of 'I2' making a transition. The propagation delay is labeled as “TP” in Figure 2.
(2) Contamination Delay (Pdmin): Contamination delay is a term used in digital circuit design to refer to the minimum time it takes for a change in the input of a logic gate to produce a change in its output. In other words, it is the minimum delay required for a signal transition at the input of a gate to affect the output of that gate.
In the video session I have taken an example of NOT Gate waveform as shown below through this waveform I would be able to give a clear overview of contamination and propagation delay.
Here Tcd, represents the contamination delay and Tpd represents the propagation delay.
(3) Setup time: Setup time in simple terms is the minimum time that data needs to be stable before a clock signal arrives. It ensures that the data is ready and settled before the clock edge comes, preventing potential errors in digital circuits.
Meeting setup time requirements is crucial for reliable and predictable circuit operation.
Let's elaborate a bit more:
Think of a digital system as a team of synchronized dancers, and each dancer represents a piece of information. The music playing in the background is like the clock signal that guides when everyone should move.
Now, setup time is like a rule for these dancers: they need to get into their positions and hold still for a moment before the music reaches a certain beat. It's like saying, "Get ready before the music goes 'boom.'"
If a dancer is still changing positions when the music hits that specific beat, there might be a collision or confusion in the dance routine. In digital circuits, this 'collision' could cause errors.
So, setup time is the preparation time, making sure all the dancers (data) are in place and ready to perform when the music (clock signal) says it's time to start. It's a way of keeping the dance routine, or the digital circuit, smooth and error-free.
(4) Hold time: Hold time is another important timing parameter in digital circuit design. It represents the minimum amount of time that the input data signal must remain stable after the active edge (rising or falling edge) of the clock signal to ensure proper and reliable operation of a flip-flop or latching circuit.
In simpler terms, hold time ensures that the data signal stays unchanged for a certain duration after the clock edge, allowing the flip-flop to capture and store the correct information without any interference.
If the input data changes too quickly after the clock edge, violating the hold time requirement, it can lead to a phenomenon known as hold time violation. Hold time violations can result in incorrect data being latched by the flip-flop, leading to errors and instability in the digital circuit.
So, to sum it up, hold time is like a rule that says, "Hey, data, you need to stay the way you are for at least this much time after the clock does its thing." It ensures a stable environment for data capture and storage in the digital circuit, preventing potential issues.
In the next blog i will write about :
What is setup slack and hold slack.
How to overcome from setup time violation and hold time violation.
Formula for removing setup time and hold time violation.
About the Author
Hello, readers.
I'm Gyanvir Singh, a VLSI Design professional with a Master's degree from NIT Hamirpur. My primary focus lies in designing and manufacturing drones tailored to meet specific customer needs. Alongside my role as a Design-for-Test (DFT) engineer, I maintain a blog dedicated to the VLSI industry.
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